1. Technical Field
The present disclosure relates to testing of semiconductor devices, and more particularly to a device power supply (DPS) extension circuit, a test system including the DPS extension circuit, and a method of testing semiconductor devices.
2. Discussion of the Related Art
During a semiconductor manufacturing process, a plurality of semiconductor devices may be formed on a wafer, and each portion of the wafer including a distinct semiconductor device is cut and packaged. During the manufacturing process, substantial or potential defects may be introduced in the semiconductor devices, and thus each semiconductor device needs to be tested for determining whether it is defective.
Burn-in tests are performed under severe environmental conditions to expose defects in the semiconductor devices such as integrated circuits. During the burn-in tests a portion of the semiconductor device may short causing an overcurrent. This overcurrent may cause further defects destroying the semiconductor device
FIG. 1 is a block diagram illustrating a conventional test system for testing semiconductor devices.
Referring to FIG. 1, a test system 100 includes a tester 10 and a board 20 for connecting a plurality of devices under test (DUTs) 21 to the tester 10. The DUTs are electrically coupled to the tester 10 through pads 22 of the board 20 and pads 18 of the tester 20.
The tester 10 includes a system controller 11, a plurality of device power supplies (DPSs) 12, a blocking circuit 15, and a relay controller 17.
The system controller 11 controls overall test operation, and determines whether the DUTs are defective based on detection signals from the DPSs 12.
Each DPS 12 includes a power supply circuit (PSC) 13 and a detection circuit (DET) 14. Each power supply circuit 13 included in each DPS 12 generates a power voltage and provides the power voltage to the corresponding DUT 21. Each detection circuit 14 outputs a detection signal indicating whether the corresponding DUT 21 is defective to the system controller 11. The system controller 11 controls the relay controller 17 in response to the detection signals from the DPSs 12. The relay controller 17, in response to a control signal from the system controller 11, opens relays 16 coupled to the DUTs 21 having defects, and thus power supplied to the defective DUTs is blocked.
Accordingly, in the conventional test system 100, the system controller 11 receives the detection signals from the DPSs 12, and controls the relay controller 17 in response to the received detection signals to block power supplied to the defective DUTs.
Among devices included in the tester for determining pass of fail of semiconductor products under test, the DPS is a device for providing power suitable for testing the product. The number of DPSs included in the tester is limited due to cost and size limitations of the tester.
Two DUTs may be coupled in parallel to one DPS for simultaneous testing, and the two DUTs are determined as passed or failed at the same time. In this case, since there is no means for determining which of the two DUTs is failed, the two DUTs are considered defective. Accordingly, subsequent testing is required for determining which of the two DUTs is defective, thereby reducing testing efficiency.
A plurality of semiconductor devices may be sequentially tested using a common circuit. In this case, additional circuitry is required for implementing the sequential testing, thereby increasing the test time.